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| 19-5211; Rev 2; 1/11 TION KIT EVALUA BLE AVAILA Gigabit Multimedia Serial Link Deserializer with LVDS System Interface MAX9268 General Description The MAX9268 deserializer utilizes Maxim's gigabit multimedia serial link (GMSL) technology. The MAX9268 deserializer features an LVDS system interface for reduced pin count and a smaller package, and pairs with any GMSL serializer to form a complete digital serial link for joint transmission of high-speed video, audio, and bidirectional control data. The MAX9268 allows a maximum serial payload data rate of 2.5Gbps for a 15m shielded twisted-pair (STP) cable. The deserializer operates up to a maximum output clock rate of 104MHz (3-channel LVDS) or 78MHz (4-channel LVDS). This serial link supports display panels from QVGA (320 x 240) to WXGA (1280 x 800) and higher with 24-bit color. The 3-channel mode outputs an LVDS clock, three lanes of LVDS data (21 bits), UART control signals, and one I2S audio channel consisting of three signals. The 4-channel mode outputs an LVDS clock, four lanes of LVDS data (28 bits), UART control signals, an I2S audio channel, and auxiliary control outputs. The three audio outputs form a standard I2S interface, supporting sample rates from 8kHz to 192kHz and audio word lengths of 4 to 32 bits. The embedded control channel forms a full-duplex, differential, 100kbps to 1Mbps UART link between the serializer and deserializer. An electronic control unit (ECU), or microcontroller (FC), can be located on the serializer side of the link (typical for video display), on the MAX9268 side of the link (typical for image sensing), or on both sides. In addition, the control channel enables ECU/FC control of peripherals on the remote side, such as backlight control, grayscale gamma correction, camera module, and touch screen. Base-mode communication with peripherals uses either I2C or the GMSL UART format. In addition, the MAX9268 features a bypass mode that enables full-duplex communication using custom UART formats. The GMSL serializer driver preemphasis, along with the MAX9268 channel equalizer, extends the link length and enhances the link reliability. Spread spectrum is available to reduce EMI on the LVDS and control outputs of the MAX9268. The serial line inputs comply with ISO 10605 and IEC 61000-4-2 ESD protection standards. The core supply for the MAX9268 is 3.3V. The I/O supply ranges from 1.8V to 3.3V. The MAX9268 is available in a 48-pin TQFP package (7mm x 7mm) with an exposed pad, and is specified over the -40NC to +105NC automotive temperature range. S Pairs with Any GMSL Serializer S 2.5Gbps Payload-Rate AC-Coupled Serial Link S Scrambled 8b/10b Line Coding S Supports WXGA (1280 x 800) with 24-Bit Color S 8.33MHz to 104MHz (3-Channel LVDS) or 6.25MHz Features to 78MHz (4-Channel LVDS) Output Clock S 4-Bit to 32-Bit Word Length, 8kHz to 192kHz I2S Audio Channel Supports High-Definition Audio S Embedded Half-/Full-Duplex Bidirectional Control Channel (100kbps to 1Mbps) S Two 3-Level Inputs Support 9 Device Addresses S Interrupt Supports Touch-Screen Functions for Display Panels S I2C Master for Peripherals S Equalizer for Serial Link Input S Programmable Spread Spectrum on the LVDS and Control Outputs for Reduced EMI S Serial-Data Clock Recovery Eliminates an External Clock S Automatic Data-Rate Detection Allows On-the-Fly Data-Rate Change S Built-In PRBS Generator for BER Testing of the Serial Link S ISO 10605 and IEC 61000-4-2 ESD Protection S -40NC to +105NC Operating Temperature Range S 1.8V to 3.3V I/O and 3.3V Core Supplies S Patent Pending Ordering Information PART MAX9268GCM/V+ MAX9268GCM/V+T TEMP RANGE -40NC to +105NC -40NC to +105NC PIN-PACKAGE 48 TQFP-EP* 48 TQFP-EP* /V denotes an automotive qualified product. +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. T = Tape and reel. Applications High-Resolution Automotive Navigation Rear-Seat Infotainment Megapixel Camera Systems _______________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. Gigabit Multimedia Serial Link Deserializer with LVDS System Interface MAX9268 ABSOLUTE MAXIMUM RATINGS AVDD to AGND ....................................................-0.5V to +3.9V DVDD, IOVDD to AGND .......................................-0.5V to +3.9V GND to AGND ......................................................-0.5V to +0.5V IN+, IN- to AGND .................................................-0.5V to +1.9V TXOUT__, TXCLKOUT_ to AGND ........................-0.5V to +3.9V All Other Pins to GND ......................... -0.5V to (VIOVDD + 0.5V) TXOUT__, TXCLKOUT_ Short Circuit to Ground or Supply ...............................................................Continuous Continuous Power Dissipation (TA = +70C) 48-Pin TQFP (derate 36.2mW/C above +70C)....2898.6mW Human Body Model (RD = 1.5k, CS = 100pF) (IN+, IN-) to AGND ..........................................................8kV (TXOUT__, TXCLKOUT_) to AGND .................................8kV All Other Pins to GND...................................................3.5kV IEC 61000-4-2 (RD = 330, CS = 150pF) Contact Discharge (IN+, IN-) to AGND ..................................................10kV (TXOUT__, TXCLKOUT_) to AGND............................8kV Air Discharge (IN+, IN-) to AGND ........................................................12kV (TXOUT__, TXCLKOUT_) to AGND ...............................20kV ISO 10605 (RD = 2k, CS = 330pF) Contact Discharge (IN+, IN-) to AGND ..........................................................8kV (TXOUT__, TXCLKOUT_) to AGND .................................8kV Air Discharge (IN+, IN-) to AGND ........................................................15kV (TXOUT__, TXCLKOUT_) to AGND ...............................30kV Operating Temperature Range ........................ -40C to +105C Junction Temperature .....................................................+150C Storage Temperature Range............................ -65C to +150C Lead Temperature (soldering, 10s) ................................+300C Soldering Temperature (reflow) ......................................+260C PACKAGE THERMAL CHARACTERISTICS (Note 1) 48 TQFP Junction-to-Ambient Thermal Resistance (BJA) .......27.6C/W Junction-to-Case Thermal Resistance (BJC).................2C/W Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VAVDD = VDVDD = 3.0V to 3.6V, VIOVDD = 1.7V to 3.6V, RL = 100 Q1% (differential), TA = -40NC to +105NC, unless otherwise noted. Typical values are at VAVDD = VDVDD = VIOVDD = 3.3V, TA = +25NC.) PARAMETER SYMBOL CONDITIONS MIN 0.65 x VIOVDD 0.35 x VIOVDD VIN = 0V to VIOVDD ICL = -18mA -10 +10 -1.5 VIOVDD - 0.3 VIOVDD - 0.2 0.3 0.2 15 3 20 5 25 7 35 10 39 13 63 21 mA TYP MAX UNITS SINGLE-ENDED INPUTS (BWS, INT, CDS, EQS, MS, PWDN, SSEN, DRS) High-Level Input Voltage Low-Level Input Voltage Input Current Input Clamp Voltage VIH1 VIL1 IIN1 VCL V V FA V SINGLE-ENDED OUTPUTS (WS, SCK, SD/CNTL0, CNTL1, CNTL2/MCLK) DCS = 0 High-Level Output Voltage VOH1 IOUT = -2mA DCS = 1 Low-Level Output Voltage VOL1 IOUT = 2mA VOUT = VGND, DCS = 0 VOUT = VGND, DCS = 1 DCS = 0 DCS = 1 VIOVDD = 3.0V to 3.6V VIOVDD = 1.7V to 1.9V VIOVDD = 3.0V to 3.6V VIOVDD = 1.7V to 1.9V V V Output Short-Circuit Current IOS 2 ______________________________________________________________________________________ Gigabit Multimedia Serial Link Deserializer with LVDS System Interface DC ELECTRICAL CHARACTERISTICS (continued) (VAVDD = VDVDD = 3.0V to 3.6V, VIOVDD = 1.7V to 3.6V, RL = 100 Q1% (differential), TA = -40NC to +105NC, unless otherwise noted. Typical values are at VAVDD = VDVDD = VIOVDD = 3.3V, TA = +25NC.) PARAMETER SYMBOL CONDITIONS MIN 0.7 x VIOVDD 0.3 x VIOVDD VIN = 0V to VIOVDD (Note 2) IOUT = 3mA RX/SDA, TX/SCL LOCK, ERR, GPIO_ VIOVDD = 1.7V to 1.9V VIOVDD = 3.0V to 3.6V -110 -80 +1 +1 0.4 0.3 TYP MAX UNITS I2C AND UART I/O, OPEN-DRAIN OUTPUTS (RX/SDA, TX/SCL, LOCK, ERR, GPIO_) High-Level Input Voltage Low-Level Input Voltage Input Current Low-Level Output Voltage VIH2 VIL2 IIN2 VOL2 V V FA V MAX9268 DIFFERENTIAL OUTPUT FOR REVERSE CONTROL CHANNEL (IN+, IN-) Differential High Output Peak Voltage, (VIN+) - (VIN-) Differential Low Output Peak Voltage, (VIN+) - (VIN-) DIFFERENTIAL INPUTS (IN+, IN-) Differential High Input Threshold (Peak) Voltage, (VIN+) - (VIN-) Differential Low Input Threshold (Peak) Voltage, (VIN+) - (VIN-) Input Common-Mode Voltage ((VIN+) + (VIN-))/2 Differential Input Resistance (Internal) VIDH(P) VIDL(P) VCMR RI Figure 2 Figure 2 -90 1 80 40 -40 1.3 100 1.6 130 90 mV mV V I VROH VROL No high-speed data transmission (Figure 1) No high-speed data transmission (Figure 1) 30 -60 60 -30 mV mV THREE-LEVEL LOGIC INPUTS (ADD0, ADD1) High-Level Input Voltage Low-Level Input Voltage VIH VIL ADD0 and ADD1 open or connected to a driver with output in high impedance (Note 3) ADD0 and ADD1 = high or low, PWDN = high or low ICL = -18mA Figure 3 Figure 3 Figure 3 Figure 3 1.125 250 0.7 x VIOVDD 0.3 x VIOVDD -10 +10 V V Mid-Level Input Current IINM FA Input Current Input Clamp Voltage Differential Output Voltage Change in VOD Between Complementary Output States Output Offset Voltage Change in VOS Between Complementary Output States IIN VCL VOD DVOD VOS DVOS -150 +150 -1.5 450 25 1.375 25 FA V mV mV V mV LVDS OUTPUTS (TXOUT__, TXCLKOUT_) _______________________________________________________________________________________ 3 Gigabit Multimedia Serial Link Deserializer with LVDS System Interface MAX9268 DC ELECTRICAL CHARACTERISTICS (continued) (VAVDD = VDVDD = 3.0V to 3.6V, VIOVDD = 1.7V to 3.6V, RL = 100 Q1% (differential), TA = -40NC to +105NC, unless otherwise noted. Typical values are at VAVDD = VDVDD = VIOVDD = 3.3V, TA = +25NC.) PARAMETER Output Short-Circuit Current Magnitude of Differential Output Short-Circuit Current Output High-Impedance Current POWER SUPPLY BWS = low, fTXCLKOUT_ = 16.6MHz Worst-Case Supply Current (Figure 4) Sleep-Mode Supply Current Power-Down Current IWCS BWS = low, fTXCLKOUT_ = 33.3MHz BWS = low, fTXCLKOUT_ = 66.6MHz BWS = low, fTXCLKOUT_ = 104MHz ICCS ICCZ PWDN = GND 142 153 179 212 80 19 180 200 240 280 130 70 FA FA mA SYMBOL IOS IOSD IOZ CONDITIONS VOUT = 0V or 3.6V 3.5mA LVDS output 7mA LVDS output ADD0 and ADD1 = high or low, PWDN = high or low -0.5 3.5mA LVDS output 7mA LVDS output MIN -7.5 -15 TYP MAX +7.5 +15 7.5 15 +0.5 UNITS mA mA FA AC ELECTRICAL CHARACTERISTICS (VAVDD = VDVDD = 3.0V to 3.6V, VIOVDD = 1.7V to 3.6V, RL = 100 Q1% (differential), TA = -40NC to +105NC, unless otherwise noted. Typical values are at VAVDD = VDVDD = VIOVDD = 3.3V, TA = +25NC.) PARAMETER SYMBOL CONDITIONS BWS = GND, VDRS = VIOVDD BWS = GND, DRS = GND VBWS = VIOVDD, VDRS = VIOVDD VBWS = VIOVDD, DRS = GND I2C/UART PORT TIMING Output Rise Time Output Fall Time Input Setup Time Input Hold Time SWITCHING CHARACTERISTICS 20% to 80%, CL = 10pF, DCS = 1 (Figure 6) 20% to 80%, CL = 5pF, DCS = 0 (Figure 6) VIOVDD = 1.7V to 1.9V VIOVDD = 3.0V to 3.6V VIOVDD = 1.7V to 1.9V VIOVDD = 3.0V to 3.6V 0.5 0.3 0.6 0.4 200 200 3.1 2.2 3.8 2.4 350 350 ps ps ns tR tF tSET tHOLD 30% to 70%, CL = 10pF to 100pF, 1kI pullup to IOVDD (Figure 5) 70% to 30%, CL = 10pF to 100pF, 1kI pullup to IOVDD (Figure 5) I2C only (Figure 5) I2C only (Figure 5) 20 20 100 0 150 150 ns ns ns ns MIN 8.33 16.66 6.25 12.5 TYP MAX 16.66 104 12.5 78 MHz UNITS LVDS CLOCK OUTPUTS (TXCLKOUT+, TXCLKOUT-) Clock Frequency fTXCLKOUT_ CNTL_ Output Rise-and-Fall Time tR, tF LVDS Output Rise Time LVDS Output Fall Time tR tF 20% to 80%, RL = 100I (Figure 3) 80% to 20%, RL = 100I (Figure 3) 4 ______________________________________________________________________________________ Gigabit Multimedia Serial Link Deserializer with LVDS System Interface AC ELECTRICAL CHARACTERISTICS (continued) (VAVDD = VDVDD = 3.0V to 3.6V, VIOVDD = 1.7V to 3.6V, RL = 100 Q1% (differential), TA = -40NC to +105NC, unless otherwise noted. Typical values are at VAVDD = VDVDD = VIOVDD = 3.3V, TA = +25NC.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS N/7 x tCLK N/7 x N/7 x tCLK fTXCLKOUT_ = 12.5MHz - 250 tCLK + 250 N = 0 to 6, tCLK = fTXCLKOUT_ = 33MHz 1/fTXCLKOUT_, fTXCLKOUT_ = 104MHz fTXCLKOUT_ = 78MHz (Figure 7) fTXCLKOUT_ = 104MHz LVDS Output Enable Time LVDS Output Disable Time Deserializer Delay Reverse Control-Channel Output Rise Time Reverse Control-Channel Output Fall Time Lock Time Power-Up Time I2S OUTPUT TIMING tLVEN tLVDS tSD tR tF tLOCK tPU From the last bit of the enable UART packet to VOS = 1125mV From the last bit of the enable UART packet to VOS = 0V Figure 8 (Note 4) No forward-channel data transmission (Figure 1) No forward-channel data transmission (Figure 1) Figure 9 Figure 10 fWS = 48kHz or 44.1kHz fWS = 96kHz fWS = 192kHz nWS = 16 bits, fWS = 48kHz or 44.1kHz 0.4e-3 x tWS 0.8e-3 x tWS 1.6e-3 x tWS 13e-3 x tSCK 39e-3 x tSCK 0.1 x tSCK 3 x tWS 0.3 0.4 0.35 x tSCK 0.35 x tSCK 0.5 x tSCK 0.5 x tSCK 180 180 N/7 x tCLK N/7 x N/7 x tCLK - 200 tCLK + 200 N/7 x tCLK N/7 x N/7 x tCLK - 125 tCLK + 125 N/7 x tCLK N/7 x N/7 x tCLK - 100 tCLK + 100 100 100 3540 400 400 3.6 4.1 0.5e-3 x tWS 1e-3 x tWS 2e-3 x tWS 16e-3 x tSCK 48e-3 x tSCK 0.13 x tSCK 4 x tWS 3.1 3.8 ns ns Fs Fs Bits ns ns ms ms MAX9268 LVDS Output Pulse Position tPPOSN ps WS Jitter tAJ-WS tWS = 1/fWS, rising (falling) edge to falling (rising) edge (Note 5) SCK Jitter tAJ-SCK tSCK = 1/fSCK, rising edge to rising edge Audio Skew Relative to Video SCK, SD, WS Rise-and-Fall Time SD, WS Valid Time Before SCK SD, WS Valid Time After SCK tASK tR, tF tDVB tDVA nWS = 24 bits, fWS = 96kHz nWS = 32 bits, fWS = 192kHz Video and audio synchronized 20% to 80% CL = 10pF, DCS = 1 CL = 5pF, DCS = 0 Fs ns ns ns tSCK = 1/fSCK (Figure 11) tSCK = 1/fSCK (Figure 11) Note 2: Minimum IIN due to voltage drop across the internal pullup resistor. Note 3: Measured in serial link bit times. Bit time = 1/(30 x fTXCLKOUT_) for BWS = GND. Bit time = 1/(40 x fTXCLKOUT_) for VBWS = VIOVDD. Note 4: Rising to rising-edge jitter can be twice as large. _______________________________________________________________________________________ 5 Gigabit Multimedia Serial Link Deserializer with LVDS System Interface MAX9268 Typical Operating Characteristics (VAVDD = VDVDD = VIOVDD = 3.3V, TA = +25NC, unless otherwise noted.) TOTAL SUPPLY CURRENT vs. TXCLKOUT_ FREQUENCY (3-CHANNEL MODE) MAX9268 toc01 TOTAL SUPPLY CURRENT vs. TXCLKOUT_ FREQUENCY (4-CHANNEL MODE) MAX9268 toc02 OUTPUT POWER SPECTRUM vs. TXCLKOUT_ FREQUENCY (VARIOUS MAX9268 SPREAD) -20 -30 -40 -50 -60 -70 -80 -90 -100 OUTPUT POWER SPECTRUM (dBm) TOTAL SUPPLY CURRENT (mA) TOTAL SUPPLY CURRENT (mA) 200 190 180 170 160 150 140 5 PRBS PATTERN ALL EQUALIZER MODES ALL SPREAD MODES 200 190 180 170 160 150 140 PRBS PATTERN ALL EQUALIZER MODES ALL SPREAD MODES fTXCLKOUT_ = 33MHz 0% SPREAD 2% SPREAD 30.5 31.5 32.5 33.5 4% SPREAD 34.5 35.5 25 45 65 85 105 5 20 35 50 65 80 TXCLKOUT_ FREQUENCY (MHz) TXCLKOUT_ FREQUENCY (MHz) TXCLKOUT_ FREQUENCY (MHz) OUTPUT POWER SPECTRUM vs. TXCLKOUT_ FREQUENCY (VARIOUS MAX9268 SPREAD) MAX9268 toc04 MAXIMUM TXCLKOUT_ FREQUENCY vs. STP CABLE LENGTH (BER < 10-9) MAX9268 toc05 MAXIMUM TXCLKOUT_ FREQUENCY vs. ADDITIONAL DIFFERENTIAL CL (BER < 10-9) MAXIMUM TXCLKOUT_ FREQUENCY (MHz) OUTPUT POWER SPECTRUM (dBm) -20 -30 -40 -50 -60 -70 -80 -90 -100 61 63 65 MAXIMUM TXCLKOUT_ FREQUENCY (MHz) fTXCLKOUT_ = 66MHz 0% SPREAD 10m STP CABLE 100 80 60 40 20 0 100 80 60 40 20 0 OPTIMUM PE/EQ SETTINGS NO PE, 10.7dB EQUALIZATION NO PE, 5.2dB EQUALIZATION BER CAN BE AS LOW AS 10-12 FOR CABLE LENGTHS LESS THAN 10m 0 5 10 15 20 OPTIMUM PE/EQ SETTINGS NO PE, 10.7dB EQUALIZATION NO PE, 5.2dB EQUALIZATION BER CAN BE AS LOW AS 10-12 FOR CL < 4pF FOR OPTIMUM PE/EQ SETTINGS 0 2 4 6 8 10 ADDITIONAL DIFFERENTIAL LOAD CAPACITANCE (pF) 2% SPREAD 4% SPREAD 67 69 71 TXCLKOUT_ FREQUENCY (MHz) STP CABLE LENGTH (m) 6 ______________________________________________________________________________________ MAX9268 toc06 -10 120 120 MAX9268 toc03 210 210 -10 Gigabit Multimedia Serial Link Deserializer with LVDS System Interface Pin Configuration TXCLKOUTTXCLKOUT+ TXOUT3TXOUT0TXOUT0+ TXOUT1TXOUT1+ AVDD TXOUT2TXOUT2+ TXOUT3+ AGND MAX9268 TOP VIEW 36 35 34 33 32 31 30 29 28 27 26 25 AGND GND IOVDD ADD0 ADD1 LOCK ERR MS SSEN DRS AVDD AGND 37 38 39 40 41 42 43 44 45 46 47 48 24 23 22 21 20 19 18 17 16 15 14 13 AGND AVDD GND IOVDD CNTL2/MCLK CNTL1 SD/CNTL0 SCK WS PWDN TX/SCL RX/SDA MAX9268 EP + 1 2 3 4 5 6 7 8 9 10 11 12 CDS GPIO0 EQS GPIO1 DVDD INAGND BWS INT IN+ AVDD TQFP GND Pin Description PIN 1 2 NAME BWS INT FUNCTION Bus-Width Select. Output width selection requires external pulldown or pullup resistor. Set BWS = low for 3-channel mode. Set BWS = high for 4-channel mode. Interrupt Input. Requires external pulldown or pullup resistor. A transition on the MAX9268's INT input toggles the GMSL serializer's INT output. Control Direction Selection. Control link direction selection input requires external pulldown or pullup resistor. Set CDS = low for FC on the GMSL serializer side of the serial link. Set CDS = high for FC on the MAX9268 side of the serial link. General-Purpose I/O 0. Open-drain, general-purpose input/output with internal 60kI (typ) pullup resistor to IOVDD. GPIO0 is high impedance during power-up and when PWDN = low. 3.3V Analog Power Supply. Bypass AVDD to AGND with 0.1FF and 0.001FF capacitors as close as possible to the device with the smaller capacitor closest to AVDD. Differential CML Input. Differential input of the serial link. Analog Ground Equalizer Select Input. EQS requires external pulldown or pullup resistor. The state of EQS latches upon power-up or when resuming from power-down mode (PWDN = low). Set EQS = low for 10.7dB equalizer boost (EQTUNE = 1001). Set EQS = high for 5.2dB equalizer boost (EQTUNE = 0100). 3 CDS 4 5, 23, 32, 47 6, 7 8, 24, 31, 37, 48 GPIO0 AVDD IN+, INAGND 9 EQS _______________________________________________________________________________________ 7 Gigabit Multimedia Serial Link Deserializer with LVDS System Interface MAX9268 Pin Description (continued) PIN 10 11 12, 22, 38 13 NAME GPIO1 DVDD GND RX/SDA FUNCTION General-Purpose I/O 1. Open-drain general-purpose input/output with internal 60kI (typ) pullup resistor to IOVDD. GPIO1 is high impedance during power-up and when PWDN = low. 3.3V Digital Power Supply. Bypass DVDD to GND with 0.1FF and 0.001FF capacitors as close as possible to the device with the smaller capacitor closest to DVDD. Digital and I/O Ground Receive/Serial Data. UART receive or I2C serial-data input/output with internal 30kI (typ) pullup to IOVDD. In UART mode, RX/SDA is the Rx input of the MAX9268's UART. In I2C mode, RX/SDA is the SDA input/output of the MAX9268's I2C master. Transmit/Serial Clock. UART transmit or I2C serial-clock output with internal 30kI (typ) pullup to IOVDD. In UART mode, TX/SCL is the Tx output of the MAX9268's UART. In I2C mode, TX/ SCL is the SCL output of the MAX9268's I2C master. Power-Down. Active-low power-down input requires external pulldown or pullup resistor. I2S Word-Select Output I2S Serial-Clock Output I2S Serial-Data/Control Output. Disable I2S to use SD/CNTL0 as an additional control output. Control Output 1. CNTL1 is not active in 3-channel mode and remains low. To use CNTL1, drive BWS high (4-channel mode) and set DISCNTL = 0. CNTL1 is mapped from DOUT27. Control 2/MCLK Output. CNTL2/MCLK is not active in 3-channel mode and remains low. To use CNTL2/MCLK, drive BWS high (4-channel mode). CNTL2/MCLK is mapped from DOUT28. CNTL/MCLK can also be used to output MCLK (see the Additional MCLK Output for Audio Applications section). I/O Supply Voltage. 1.8V to 3.3V logic I/O power supply. Bypass IOVDD to GND with 0.1FF and 0.001FF capacitors as close as possible to the device with the smaller capacitor closest to IOVDD. Differential LVDS Data Outputs. Set BWS = low (3-channel mode) to use TXOUT0_ to TXOUT2_. Set BWS = high (4-channel mode) to use TXOUT0_ to TXOUT3_. Differential LVDS Output for the LVDS Clock Address Selection Input 0. Three-level input to select the MAX9268's device address (see Table 2). The state of ADD0 latches upon power-up or when resuming from power-down mode (PWDN = low). Address Selection Input 1. Three-level input to select the MAX9268's device address (see Table 2). The state of ADD1 latches upon power-up or when resuming from power-down mode (PWDN = low). Open-Drain Lock Output with Internal 60kI (typ) Pullup to IOVDD. LOCK = high indicates PLLs are locked with correct serial-word-boundary alignment. LOCK = low indicates PLLs are not locked or incorrect serial-word-boundary alignment. LOCK remains low when the configuration link is active. LOCK is high impedance when PWDN = low. Active-Low, Open-Drain Video Data Error Output with Internal 60kI (typ) Pullup to IOVDD. ERR goes low when the number of decoding errors during normal operation exceeds a programmed error threshold, or when at least one PRBS error is detected during PRBS test. ERR is high impendence when PWDN = low. 14 15 16 17 18 19 TX/SCL PWDN WS SCK SD/CNTL0 CNTL1 20 CNTL2/MCLK 21, 39 25, 26, 29, 30, 33-36 27, 28 IOVDD TXOUT_+, TXOUT_TXCLKOUT+, TXCLKOUTADD0 40 41 ADD1 42 LOCK 43 ERR 8 ______________________________________________________________________________________ Gigabit Multimedia Serial Link Deserializer with LVDS System Interface Pin Description (continued) PIN 44 NAME MS FUNCTION Mode Select. Control link mode-selection input requires an external pulldown or pullup resistor. Set MS = low to select base mode. Set MS = high to select bypass mode. Spread-Spectrum Enable. Serial link spread-spectrum enable input requires an external pulldown or pullup resistor. The state of SSEN latches upon power-up or when resuming from power-down mode (PWDN = low). Set SSEN = high for Q2% spread spectrum on the LVDS and control outputs. Set SSEN = low to use the LVDS and control outputs without spread spectrum. Data-Rate Select. Data-rate range-selection input requires an external pulldown or pullup resistor. The state of DRS latches upon power-up or when resuming from power-down mode (PWDN = low). Set DRS = high for TXCLKOUT_ frequencies of 8.33MHz to 16.66MHz (3-channel mode), or 6.25MHz to 12.5MHz (4-channel mode). Set DRS = low for TXCLKOUT_ frequencies of 16.66MHz to 104MHz (3-channel mode), or 12.5MHz to 78MHz (4-channel mode). Exposed Pad. EP internally connected to AGND. MUST externally connect EP to the plane supplying AGND for proper thermal and electrical performance. MAX9268 45 SSEN 46 DRS -- EP Functional Diagram IN+ TXCLKOUT+/7x PLL SSPLL CLK DIV CDR PLL Rx/EQ IN- TXOUT0+/- RGB[17:0] HS RGB HS VIDEO VS DE TXOUT1+/PARALLEL TO LVDS TXOUT2+/- VS DE RGB[23:18] (4-CH) SERIAL TO PARALLEL TXOUT3+/- RES/CNTL1 (4-CH) FIFO CNTL1/RES CNTL2 8b/10b DECODE/ UNSCRAMBLE Tx CNTL1 (4-CH) AUDIO CNTL2/MCLK (4-CH) ACB FCC REVERSE CONTROL CHANNEL MAX9268 UART/I2C SD/CNTL0 SCK WS TX/SCL RX/SDA _______________________________________________________________________________________ 9 Gigabit Multimedia Serial Link Deserializer with LVDS System Interface MAX9268 IN+ RL/2 MAX9268 VOD REVERSE CONTROL-CHANNEL TRANSMITTER INVCMR RL/2 IN+ VCMR IN- IN- IN+ VROH 0.9 x VROH (IN+) - (IN-) 0.1 x VROH 0.1 x VROL tR 0.9 x VROL VROL tF Figure 1. Reverse Control-Channel Output Parameters RL/2 IN+ RL/2 VIN+ + _ VIN+ _ CIN VID(P) IN_ CIN VID(P) = | VIN+ - VIN- | VCMR = (VIN+ + VIN-)/2 Figure 2. Test Circuit for Differential Input Measurement 10 _____________________________________________________________________________________ Gigabit Multimedia Serial Link Deserializer with LVDS System Interface MAX9268 TXOUT_+ TXCLKOUT+ VOD TXOUT_-, TXCLKOUTVOS RL/2 GND RL/2 TXOUT_TXCLKOUTTXOUT_+ TXCLKOUT+ ((TXOUT_+) + (TXOUT_-))/2 ((TXCLKOUT+) + (TXCLKOUT-))/2 VOS(-) VOS(+) VOS(-) DVOS = |VOS(+) - VOS(-)| VOD(+) VOD = 0V VOD(-) (TXOUT_+) - (TXOUT_-) (TXCLKOUT+) - (TXCLKOUT-) tR DVOD = |VOD(+) - VOD(-)| tF VOD(-) Figure 3. LVDS Output Parameters TXCLKOUT+ TXCLKOUTTXOUT0+ TO TXOUT3+ TXOUT0- TO TXOUT3- CNTL_ Figure 4. Worst-Case Pattern Output tR TX/ SCL tF tHOLD tSET RX/ SDA P S S P Figure 5. I2C Timing Parameters ______________________________________________________________________________________ 11 Gigabit Multimedia Serial Link Deserializer with LVDS System Interface MAX9268 (TXCLKOUT+) (TXCLKOUT-) CL MAX9268 SINGLE-ENDED OUTPUT LOAD 0.8 x VI0VDD (TXOUT_+) (TXOUT_-) tPPOS0 tPPOS1 tPPOS2 tPPOS3 0.2 x VI0VDD tR tF tPPOS4 tPPOS5 tPPOS6 Figure 6. Single-Ended Output Rise-and-Fall Times Figure 7. LVDS Output Pulse Position Measurement FIRST BIT IN+/IN- N N+1 N+2... EXPANDED TIME SCALE FIRST BIT N-1 N IN+ - IN- TXOUT_+/ TXOUT_- tLOCK TXCLKOUT+/- LOCK VOH tSD PWDN MUST BE HIGH Figure 8. Deserializer Delay Figure 9. Lock Time IN+/WS PWDN VIH1 SCK tDVA tDVB tR tPU LOCK VOH SD tDVB tDVA tF Figure 10. Power-Up Delay Figure 11. Output I2S Timing Parameters 12 _____________________________________________________________________________________ Gigabit Multimedia Serial Link Deserializer with LVDS System Interface Detailed Description The MAX9268 deserializer with LVDS system interface utilizes Maxim's GMSL technology. The MAX9268 deserializer pairs with any GMSL serializer to form a complete digital serial link for joint transmission of highspeed video, audio, and bidirectional control data. The MAX9268 allows a maximum serial payload data rate of 2.5Gbps for greater than 15m of STP cable. The deserializer operates up to 104MHz for 3-channel LVDS or 78MHz for 4-channel LVDS. The operating frequency range supports display panels from QVGA (320 x 240) up to WXGA (1280 x 800) and higher with 24-bit color. The 3-channel mode outputs an LVDS clock, three lanes of LVDS data (21 bits), UART control signals, and one I2S audio channel (consisting of three signals). The 4-channel mode outputs an LVDS clock, four lanes of LVDS data (28 bits), UART control signals, one I2S audio channel, and control signals. The I2S interface supports sample rates from 8kHz to 192kHz and audio word lengths of 4 to 32 bits. The embedded control channel forms a full-duplex, differential, 100kbps to 1Mbps UART link between the serializer and deserializer. An ECU or FC can be located on the serializer side of the link (typical for video display), on the MAX9268 side of the link (typical for image sensing), or on both sides. In addition, the control channel enables ECU/FC control of peripherals in the remote side, such as backlight control, grayscale Gamma correction, camera module, and touch screen. Base-mode communication with peripherals uses either I2C or the GMSL UART format. A bypass mode enables full-duplex communication using custom UART formats. The MAX9268 channel equalizer, along with the serializer preemphasis, extends the link length and enhances the link reliability. Spread spectrum is available to reduce EMI on the LVDS and control outputs of the MAX9268. The serial input complies with ISO 10605 and IEC 61000-4-2 ESD protection standards. The FC configures various operating conditions of the GMSL serializer and the MAX9268 through internal registers. The default device addresses are stored in registers 0x00 and 0x01 of both the GMSL serializer and the MAX9268 (Table 1). Write to the 0x00 and 0x01 registers in both devices to change the device address of the GMSL serializer or the MAX9268. MAX9268 Register Mapping Table 1. Power-Up Default Register Map (see Table 12) REGISTER ADDRESS (hex) 0x00 POWER-UP DEFAULT (hex) 0x40, 0x44, 0x48 0x80, 0x84, 0x88, 0xC0, 0xC4, 0xC8 0x50, 0x54, 0x58, 0x90, 0x94, 0x98, 0xD0, 0xD4, 0xD8 POWER-UP DEFAULT SETTINGS (MSB FIRST) SERID = XX00XX0, serializer device address is determined by ADD1 and ADD0 (Table 2) RESERVED = 0 DESID =XX01XX0, deserializer device address is determined by ADD1 and ADD0 (Table 2) RESERVED = 0 SS = 00 (SSEN = low), SS = 01 (SSEN = high), spread-spectrum settings depend on SSEN pin state at power-up RESERVED = 0 AUDIOEN = 1, I2S channel enabled PRNG = 11, automatically detect the pixel clock range SRNG = 11, automatically detect serial-data rate AUTOFM = 00, calibrate spread-modulation rate only once after locking RESERVED = 0 SDIV = 00000, autocalibrate sawtooth divider 0x01 0x02 0x1F or 0x5F 0x03 0x00 ______________________________________________________________________________________ 13 Gigabit Multimedia Serial Link Deserializer with LVDS System Interface MAX9268 Table 1. Power-Up Default Register Map (see Table 12) (continued) REGISTER ADDRESS (hex) POWER-UP DEFAULT (hex) POWER-UP DEFAULT SETTINGS (MSB FIRST) LOCKED = 0, LOCK output is low (read only) OUTENB = 0, outputs enabled PRBSEN = 0, PRBS test disabled SLEEP = 0 or 1, SLEEP setting default depends on CDS and MS pin state at power-up (see the Link Startup Procedure section) INTTYPE = 00, base mode uses I2C REVCCEN = 1, reverse control channel active (sending) FWDCCEN = 1, forward control channel active (receiving) I2CMETHOD = 0, I2C master sends the register address HPFTUNE = 01, 3.75MHz equalizer highpass cutoff frequency PDHF = 0, high-frequency boosting disabled EQTUNE = 0100 (EQS = high, 5.2dB), EQTUNE = 1001 (EQS = low, 10.7dB), EQTUNE default setting depends on EQS pin state at power-up RESERVED = 0 AUTORST = 0, error registers/output autoreset disabled DISINT = 0, INT transmission enabled INT = 0, INT output is low (read only) GPIO1OUT = 1, GPIO1 output set to high GPIO1 = 1, GPIO1 input = high (read only) GPIO0OUT = 1, GPIO0 output set to high GPIO0 = 1, GPIO0 input = high (read only) RESERVED = 01010100 RESERVED = 00110000 RESERVED = 11001000 RESERVED = 00010010 RESERVED = 00100000 ERRTHR = 00000000, error threshold set to zero for decoding errors DECERR = 00000000, zero decoding errors detected PRBSERR = 00000000, zero PRBS errors detected MCLKSRC = 0, MCLK is derived from PCLK (see Table 5) MCLKDIV = 0000000, MCLK output is disabled RESERVED = XXX RESERVED = 10000 RESERVED = 00 FORCELVDS = 0, normal LVDS operation DCS = 0, normal CMOS driver current strength DISCNTL1 = 0, serial-data bit 27 is mapped to CNTL1 DISRES = 0, serial-data bit 27 is mapped to RES ILVDS = 01, 3.5mA LVDS output current 0x04 0x03 or 0x13 0x05 0x24 or 0x29 0x06 0x0F 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x12 0x13 0x54 0x30 0xC8 0x12 0x20 0x00 0x00 (read only) 0x00 (read only) 0x00 0xX0 0x14 0x01 14 _____________________________________________________________________________________ Gigabit Multimedia Serial Link Deserializer with LVDS System Interface Table 1. Power-Up Default Register Map (see Table 12) (continued) REGISTER ADDRESS (hex) 0x1E POWER-UP DEFAULT (hex) 0x04 (read only) 0x0X (read only) POWER-UP DEFAULT SETTINGS (MSB FIRST) ID = 00000100, device ID is 0x04 RESERVED = 000 CAPS = 0, not HDCP capable REVISION = XXXX MAX9268 0x1F X = Don't care. Table 2. Deserializer Device Address Defaults (Register 0x01) PIN ADD1 Low Low Low High High High Open Open Open ADD0 Low High Open Low High Open Low High Open D7 1 1 1 1 1 1 0 0 0 D6 0 0 0 1 1 1 1 1 1 D5 0 0 0 0 0 0 0 0 0 DEVICE ADDRESS* (bin) D4 X** X** X** X** X** X** X** X** X** D3 0 0 1 0 0 1 0 0 1 D2 0 1 0 0 1 0 0 1 0 D1 0 0 0 0 0 0 0 0 0 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W SERIALIZER DEVICE ADDRESS* (hex) 80 84 88 C0 C4 C8 40 44 48 DESERIALIZER DEVICE ADDRESS* (hex) 90 94 98 D0 D4 D8 50 54 58 *ADD0 and ADD1 affect the default device address values stored in the MAX9268 only. The default device address values stored in the GMSL serializer may differ (see the 3-Level Inputs for Default Device Address section). **X = 0 for the serializer address, X = 1 for the deserializer address. ______________________________________________________________________________________ 15 Gigabit Multimedia Serial Link Deserializer with LVDS System Interface MAX9268 The LVDS output has two selectable widths: 3-channel and 4-channel. The MAX9268 outputs 3- or 4-channel LVDS (Table 3). Serial data is mapped to outputs on the MAX9268 according to Figures 12 and 13. In 3-channel mode, TXOUT3_ and CNTL1, CNTL2/MCLK are not available. For both modes, the SD/CNTL0, SCK, and WS pins are for I2S audio when audio is enabled. With audio disabled, SD/CNTL0 becomes control signal CNTL0. The MAX9268 outputs clock rates from 8.33MHz to 104MHz for 3-channel mode and 6.25MHz to 78MHz for 4-channel mode. The GMSL high-speed serial link uses CML signaling with programmable preemphasis and AC-coupling. The GMSL deserializer uses AC-coupling and programmable channel equalization. When using both the preemphasis and equalization, including internally generated over- Typical Bitmapping and Bus-Width Selection head bits, the GMSL link operates up to 3.125Gbps over STP cable lengths of 15m or greater. The payload data rate, which is the data rate available to the user or the data rate after subtracting overhead, is 2.5Gbps. The GMSL serializer scrambles and encodes the input data and sends the 8b/10b coded signal through the serial link. The MAX9268 deserializer recovers the embedded serial clock and then samples, decodes, and descrambles before outputting the data. Figures 14 and 15 show the serial-data packet format after unscrambling and 8b/10b decoding. In 3-channel or 4-channel mode, 21 or 28 bits map to the TXOUT_ _ LVDS outputs. Serialdata bits 27 and 28 map to control outputs in 4-channel mode. The audio channel bit (ACB) contains an encoded audio signal derived from the three I2S signals (SD/ CNTL0, SCK, and WS). The forward control-channel (FCC) bit carries the forward control data. The last bit (PCB) is the parity bit of the previous 23 or 31 bits. Serial Link Signaling and Data Format Table 3. Bus-Width Selection Using BWS OUTPUT BITS 3-CHANNEL MODE (BWS = LOW) TYPICAL BITMAPPING DOUT[0:5] DOUT[6:11] DOUT[12:17] DOUT[18:20] DOUT[21:22] DOUT[23:24] DOUT[25:26] DOUT27 DOUT28 R[0:5] G[0:5] B[0:5] HS, VS, DE Not used Not used Not used Not used Not used AUXILIARY SIGNALS MAPPING -- -- -- -- Not used Not used Not used Not used Not used 4-CHANNEL MODE (BWS = HIGH) TYPICAL BITMAPPING R[0:5] G[0:5] B[0:5] HS, VS, DE R6, R7 G6, G7 B6, B7 RES* -- -- AUXILIARY SIGNALS MAPPING -- -- -- -- -- -- -- CNTL1* CNTL2/MCLK SD/CNTL0 SD -- SD/CNTL0 *See the Reserved Bit (RES)/CNTL1 section for details. 16 _____________________________________________________________________________________ Gigabit Multimedia Serial Link Deserializer with LVDS System Interface MAX9268 TXCLKOUTTXCLKOUT+ CYCLE N-1 CYCLE N DOUT5 DOUT4 DOUT3 DOUT2 DOUT1 DOUT0 TXOUT0+ /TXOUT0- DOUT1 DOUT0 DOUT6 TXOUT1+/TXOUT1- DOUT8 DOUT7 DOUT13 DOUT12 DOUT11 DOUT10 DOUT9 DOUT8 DOUT7 TXOUT2+/TXOUT2- DOUT15 DOUT14 DOUT20 DOUT19 DOUT18 DOUT17 DOUT16 DOUT15 DOUT14 TXOUT3+/TXOUT3- DOUT22 DOUT21 DOUT27 DOUT26 DOUT25 DOUT24 DOUT23 DOUT22 DOUT21 CNTL1 DOUT27 CNTL2/MCLK DOUT28 SD/CNTL0 *ONLY WHEN I2S IS DISABLED. SD* Figure 12. LVDS Output Timing TXCLKOUTTXCLKOUT+ CYCLE N-1 CYCLE N TXOUT0+/TXOUT0- R1 R0 G0 R5 R4 R3 R2 R1 R0 TXOUT1+/TXOUT1- G2 G1 B1 B0 G5 G4 G3 G2 G1 TXOUT2+/TXOUT2- B3 B2 DE VS HS B5 B4 B3 B2 TXOUT3+/TXOUT3- R7 R6 RES B7 B6 G7 G6 R7 R6 Figure 13. Typical Panel Clock and Bit Assignment ______________________________________________________________________________________ 17 Gigabit Multimedia Serial Link Deserializer with LVDS System Interface MAX9268 24 BITS DOUT0 DOUT1 R0 R1 DOUT17 DOUT18 DOUT19 DOUT20 ACB B5 LVDS DATA (3 CHANNELS) HS VS DE FCC PCB AUDIO CHANNEL BIT FORWARD CONTROLCHANNEL BIT PACKET PARITY CHECK BIT NOTE: TYPICAL LOCATIONS OF THE RGB DATA AND CONTROL SIGNALS. Figure 14. 3-Channel Mode Serial Link Data Format 32 BITS DOUT0 DOUT1 R0 R1 DOUT17 DOUT18 DOUT19 DOUT20 DOUT21 DOUT22 DOUT23 DOUT24 DOUT25 DOUT26 DOUT27 DOUT28 ACB B5 LVDS DATA (TXOUT[2:0]_) HS VS DE R6 R7 G6 G7 LVDS DATA (TXOUT3_) RES/CNTL1* B6 B7 CNTL2 FCC PCB AUDIO CHANNEL/CNTL0 BIT FORWARD CONTROLCHANNEL BIT PACKET PARITY CHECK BIT NOTE: TYPICAL LOCATIONS OF THE LVDS RGB DATA AND CONTROL SIGNALS. *DOUT27 OUTPUTS TO LVDS DATA (TXOUT3_) AND/OR EXTERNAL PIN (CNTL1). Figure 15. 4-Channel Mode Serial Link Data Format In 4-channel mode, the MAX9268 deserializes serialdata bit 27 to both RES and CNTL1 by default (both DISCNTL and DISRES = 0). Setting DISRES (D2 of register 0x14) = 1 forces RES low. Setting DISCNTL1 (D3 of register 0x14) = 1 forces CNTL1 low. The GMSL serializer uses the reverse control channel to receive I2C/UART and interrupt signals from the MAX9268 in the opposite direction of the video stream. The reverse control channel and forward video data coexist on the same twisted pair forming a bidirectional link. The reverse control channel operates independently from the forward control channel. The reverse control channel is available 500Fs after power-up. The GMSL serializer temporarily disables the reverse control Reserved Bit (RES)/CNTL1 channel for 350Fs after starting/stopping the forward serial link. The MAX9268 uses the DRS input to set the TXCLKOUT_ frequency. Set DRS high for a TXCLKOUT_ frequency of 6.25MHz to 12.5MHz (4-channel mode), or 8.33MHz to 16.66MHz (3-channel mode). Set DRS low for normal operation with a TXCLKOUT_ frequency of 12.5MHz to 78MHz (4-channel mode), or 16.66MHz to 104MHz (3-channel mode). The I2S audio channel supports audio sampling rates from 8kHz to 192kHz and audio word lengths from 4 bits to 32 bits. The audio bit clock (SCK) does not have to be synchronized with TXCLKOUT_. The GMSL serializer automatically encodes audio data into a single bit stream Data-Rate Selection Reverse Control Channel Audio Channel 18 _____________________________________________________________________________________ Gigabit Multimedia Serial Link Deserializer with LVDS System Interface synchronous with TXCLKOUT_. The MAX9268 deserializer decodes the audio stream and stores audio words in a FIFO. Audio rate detection uses an internal oscillator to continuously determine the audio data rate and output the audio in I2S format. The audio channel is enabled by default. When the audio channel is disabled, the audio data input (SD) on the serializer becomes a control input (CNTL0) and SD/CNTL0 becomes a control output on the deserializer. Low TXCLKOUT_ frequencies limit the maximum audio sampling rate. Table 4 lists the maximum audio sampling rate for various TXCLKOUT_ frequencies. Spread-spectrum settings do not affect the I2S data rate or WS clock frequency. output on CNTL2/MCLK at the expense of one less control line in 4-channel mode (3-channel mode is not affected). By default, CNTL2/MCLK operates as a control data output, and MCLK is turned off. Set MCLKDIV (MAX9268 register 0x12, D[6:0]) to a nonzero value to enable the MCLK output. Set MCLKDIV to 0x00 to disable MCLK and set CNTL2/MCLK as a control data output. The output MCLK frequency is: where: fMCLK = fSRC MCLKDIV MAX9268 fSRC = the MCLK source frequency (Table 5) MCLKDIV = the divider ratio from 1 to 127 Choose MCLKDIV values such that fMCLK is not greater than 60MHz. MCLK frequencies derived from TXCLKOUT_ (MSCLKSRC = 0) are not affected by spread-spectrum settings in the MAX9268. However, enabling spread spectrum in the GMSL serializer introduces spread spectrum into MCLK. Spread-spectrum settings of either device do not affect MCLK frequencies derived from the internal oscillator. The internal oscillator frequency ranges from 100MHz to 150MHz over all process corners and operating conditions. Some audio DACs such as the MAX9850 do not require a synchronous main clock (MCLK), while other DACs require MCLK to be a specific multiple of WS. If the audio DAC chip needs the MCLK to be a multiple of WS, use an external PLL to regenerate the required MCLK from WS or SCK. For audio applications that have WS synchronous to TXCLKOUT_, the MAX9268 provides a divided clock Additional MCLK Output for Audio Applications Table 4. Maximum Audio WS Frequency (kHz) for Various TXCLKOUT_ Frequencies WORD LENGTH (BITS) 8 16 18 20 24 32 TXCLKOUT_ FREQUENCY (DRS = LOW) (MHz) 12.5 > 192 > 192 185.5 174.6 152.2 123.7 15 > 192 > 192 > 192 > 192 182.7 148.4 16.6 > 192 > 192 > 192 > 192 > 192 164.3 > 20 > 192 > 192 > 192 > 192 > 192 > 192 6.25 > 192 > 192 185.5 174.6 152.2 123.7 TXCLKOUT_ FREQUENCY (DRS = HIGH) (MHz) 7.5 > 192 > 192 > 192 > 192 182.7 148.4 8.33 > 192 > 192 > 192 > 192 > 192 164.3 > 10 > 192 > 192 > 192 > 192 > 192 > 192 Table 5. fSRC Settings MCLKSRC SETTING (REGISTER 0x12, D7) DATA-RATE SETTING High speed 0 Low speed 1 -- BUS-WIDTH SETTING 3-channel mode 4-channel mode 3-channel mode 4-channel mode -- MCLK SOURCE FREQUENCY (fSRC) 3 x fTXCLKOUT_ 4 x fTXCLKOUT_ 6 x fTXCLKOUT_ 8 x fTXCLKOUT_ Internal oscillator (120MHz, typ) 19 ______________________________________________________________________________________ Gigabit Multimedia Serial Link Deserializer with LVDS System Interface MAX9268 The control channel is available for the FC to send and receive control data over the serial link simultaneously with the high-speed data, to program registers on the link serializer/deserializer or to program peripherals. Configuring the CDS pin allows a FC to control the link from the side of the serializer or deserializer, or with dual FCs from both sides, to support a wide variety of applications. The control channel runs in base mode or bypass mode according to the mode-selection (MS) input of the device connected to the FC. In base mode, the control-channel transactions are half-duplex and in bypass mode they are full-duplex. Base Mode In base mode the FC is the host, and in order to access the registers of the serializer or deserializer it must use the GMSL UART format and protocol. The FC accesses peripherals with an I2C interface by sending GMSL UART packets, which are converted to I2C by the serializer or deserializer on the remote side of the link. The FC communicates with a UART peripheral in base mode (through INTTYPE register settings) using the GMSL UART protocol. The device addresses of the GMSL serializer and MAX9268 in base mode are programmable. The default MAX9268 device address is determined by ADD0 and ADD1 upon power-up, or after returning from a powerdown state (Table 2). When the peripheral interface uses I2C (default), the GMSL serializer/MAX9268 convert packets to I2C that have device addresses different from those of the GMSL serializer or MAX9268. The converted I2C bit rate is the same as the original UART bit rate. The GMSL serializer embeds control signals going to the MAX9268 in the high-speed forward link. The MAX9268 uses a proprietary differential line coding to send signals Control Channel and Register Programming back towards the serializer. The speed of the control channel ranges from 100kbps to 1Mbps in both directions. The GMSL serializer and MAX9268 deserializer automatically detect the control-channel bit rate in base mode. Packet bit rates can vary up to 3.5x from the previous bit rate (see the Changing the Clock Frequency section). Figure 16 shows the UART protocol for writing and reading in base mode between the FC and the GMSL serializer/MAX9268. Figure 17 shows the UART data format. Figures 18 and 19 detail the formats of the SYNC byte (0x79) and the ACK byte (0xC3). The FC and the connected slave chip generate the SYNC byte and ACK byte, respectively. Events such as device wake-up and interrupt generate transitions on the control channel that should be ignored by the FC. Data written to the GMSL serializer/MAX9268 registers do not take effect until after the acknowledge byte is sent. This allows the FC to verify write commands received without error, even if the result of the write command directly affects the serial link. The slave uses the SYNC byte to synchronize with the host UART data rate automatically. If the INT or MS inputs of the MAX9268 toggle while there is control-channel communication, the control-channel communication can be corrupted since INT has priority on the control channel. In the event of a missed acknowledge, the FC should assume there was an error in the packet when the slave device receives it, or that an error occurred during the response from the slave device. In base mode, the FC must keep the UART Tx/Rx lines high for 16 bit times before sending a new packet. As shown in Figure 20, the remote-side device converts the packets going to or coming from the peripherals from the UART format to the I2C format and vice versa. The remote device removes the byte number count and adds or receives the ACK between the data bytes of I2C. The I2C's data rate is the same as the UART data rate. WRITE DATA FORMAT SYNC DEV ADDR + R/W REG ADDR NUMBER OF BYTES MASTER WRITES TO SLAVE BYTE 1 BYTE N ACK MASTER READS FROM SLAVE READ DATA FRMAT SYNC DEV ADDR + R/W REG ADDR NUMBER OF BYTES ACK BYTE 1 BYTE N MASTER WRITES TO SLAVE MASTER READS FROM SLAVE Figure 16. GMSL UART Protocol for Base Mode 20 _____________________________________________________________________________________ Gigabit Multimedia Serial Link Deserializer with LVDS System Interface MAX9268 1 UART FRAME START D0 D1 D2 D3 D4 D5 D6 D7 PARITY STOP FRAME 1 FRAME 2 FRAME 3 STOP START STOP START Figure 17. GMSL UART Data Format for Base Mode D0 START 1 D1 0 D2 0 D3 1 D4 1 D5 1 D6 1 D7 0 PARITY STOP START D0 1 D1 1 D2 0 D3 0 D4 0 D5 0 D6 1 D7 1 PARITY STOP Figure 18. SYNC Byte (0x79) Figure 19. ACK Byte (0xC3) UART-TO-I2C CONVERSION OF WRITE PACKET (I2CMETHOD = 0) FC GMSL SERIALIZER/MAX9268 11 SYNC FRAME 11 DEVICE ID + WR 11 REGISTER ADDRESS 11 NUMBER OF BYTES 11 DATA 0 11 DATA N 11 ACK FRAME GMSL SERIALIZER/MAX9268 PERIPHERAL 1 S 7 DEV ID 11 WA 8 REG ADDR 1 A 8 DATA 0 1 A 8 DATA N 11 AP UART-TO-I2C CONVERSION OF READ PACKET (I2CMETHOD = 0) FC GMSL SERIALIZER/MAX9268 11 SYNC FRAME 11 DEVICE ID + RD 11 REGISTER ADDRESS 11 NUMBER OF BYTES 11 ACK FRAME 11 DATA 0 11 DATA N GMSL SERIALIZER/MAX9268 PERIPHERAL 1 S 7 DEV ID 11 WA 8 REG ADDR 11 AS 7 DEV ID 11 RA 8 DATA 0 1 A 8 DATA N 11 AP : MASTER TO SLAVE : SLAVE TO MASTER S: START P: STOP A: ACKNOWLEDGE Figure 20. Format Conversion between GMSL UART and I2C with Register Address (I2CMETHOD = 0) ______________________________________________________________________________________ 21 Gigabit Multimedia Serial Link Deserializer with LVDS System Interface Interfacing Command-Byte-Only I2C Devices The GMSL serializer and MAX9268 UART-to-I2C conversion interfaces with devices that do not require register addresses, such as the MAX7324 GPIO expander. In this mode, the I2C master ignores the register address byte and directly reads/writes the subsequent data bytes (Figure 21). Change the communication method of the I2C master using the I2CMETHOD bit. I2CMETHOD = 1 sets command-byte-only mode, while I2CMETHOD = 0 sets normal mode where the first byte in the data stream is the register address. Bypass Mode In bypass mode, the GMSL serializer/MAX9268 ignore UART communications. The FC is thereby free to communicate with the peripherals using its own UART protocol without concern that communication traffic inadvertently misprograms the GMSL serializer or MAX9268. The FC cannot access the GMSL serializer/ MAX9268 registers in this mode. Peripherals accessed through the forward control channel using the UART interface need to handle at least one TXCLKOUT_ period of jitter due to the asynchronous sampling of the UART signal by TXCLKOUT_. Set MS = high to put the control channel into bypass mode. For applications with the FC connected to the deserializer (CDS is high), there is a 1ms wait time between setting MS high and the bypass control channel being active. There is no delay time when switching to bypass mode when the FC is connected to the serializer MAX9268 (CDS = low). Bypass mode accepts bit rates down to 28kbps in the forward direction (serializer to deserializer), and 7.7kbps in the reverse direction (deserializer to serializer). See the Interrupt Control section for interrupt functionality limitations. The control-channel data pattern should not be held low longer than 100s if interrupt control is used. The INT pin of the GMSL serializer is the interrupt output and the INT pin of the MAX9268 is the interrupt input. The interrupt output on the GMSL serializer follows the transitions at the interrupt input, even during reversechannel communication or loss of lock. This interrupt function supports remote-side functions such as touchscreen peripherals, remote power-up, or remote monitoring. Interrupts that occur during periods where the reverse control channel is disabled, such as link startup/ shutdown, are automatically resent once the reverse control channel becomes available again. Bit D4 of register 0x06 in the MAX9268 also stores the interrupt input state. The INT output of the GMSL serializer is low after power-up. In addition, the FC can set the INT output of the serializer by writing to the SETINT register bit. In normal operation, the state of the interrupt output changes when the interrupt input on the MAX9268 toggles. Do not send a logic-low value longer than 100Fs in either base or bypass mode to ensure proper interrupt functionality. Interrupt Control UART-TO-I2C CONVERSION OF WRITE PACKET (I2CMETHOD = 1) FC 11 SYNC FRAME GMSL SERIALIZER/MAX9268 11 11 DEVICE ID + WR REGISTER ADDRESS PERIPHERAL 1 7 S DEV ID 11 NUMBER OF BYTES 11 DATA 0 11 DATA N 11 ACK FRAME GMSL SERIALIZER/MAX9268 11 WA 8 DATA 0 1 A 8 DATA N 11 AP FC UART-TO-I2C CONVERSION OF READ PACKET (I2CMETHOD = 1) GMSL SERIALIZER/MAX9268 11 11 11 SYNC FRAME DEVICE ID + RD REGISTER ADDRESS PERIPHERAL 11 NUMBER OF BYTES 11 ACK FRAME 11 DATA 0 11 DATA N GMSL SERIALIZER/MAX9268 1 S 7 DEV ID 11 RA 8 DATA 0 1 A 8 DATA N 11 AP : MASTER TO SLAVE : SLAVE TO MASTER S: START P: STOP A: ACKNOWLEDGE Figure 21. Format Conversion Between GMSL UART and I2C with Register Address (I2CMETHOD = 1) 22 _____________________________________________________________________________________ Gigabit Multimedia Serial Link Deserializer with LVDS System Interface The MAX9268 includes an adjustable line equalizer to further compensate cable attenuation at high frequencies. The cable equalizer has 12 selectable levels of compensation, from 2.1dB to 13dB (Table 6). The EQS input selects the default equalization level at power-up. The state of EQS is latched upon power-up or when resuming from powerdown mode. To select other equalization levels, set the corresponding register bits in the MAX9268 (0x05 D[3:0]). Use equalization in the MAX9268, together with preemphasis in the GMSL serializer, to create the most reliable link for a given cable. To reduce the EMI generated by the transitions on the serial link and outputs of the MAX9268, both the GMSL serializer and MAX9268 support spread spectrum. Turning on spread spectrum on the GMSL serializer spreads the serial data and the MAX9268 outputs. Do not enable spread for both the GMSL serializer and the MAX9268. The two selectable spread-spectrum rates at the MAX9268 outputs are Q2% and Q4% (Table 7). Set the MAX9268 SSEN input high to select 2% spread at power-up, and SSEN input low to select no spread at power-up. The state of SSEN is latched upon power-up or when resuming from power-down mode. Turning on spread spectrum on the GMSL serializer or the MAX9268 does not affect the audio data stream. Changes Line Equalizer in the GMSL serializer spread settings only affect the MAX9268 MCLK output if it is derived from TXCLKOUT_ (MCLKSRC = 0). The MAX9268 includes a sawtooth divider to control the spread-modulation rate. Autodetection or manual programming of the TXCLKOUT_ operation range guarantees a spread-spectrum modulation frequency within 20kHz to 40kHz. Additionally, manual configuration of the sawtooth divider (SDIV, 0x03 D[4:0]) allows the user to set a modulation frequency according to the TXCLKOUT_ frequency. Always keep the modulation frequency between 20kHz to 40kHz to ensure proper operation. MAX9268 Spread Spectrum The modulation rate for the MAX9268 relates to the TXCLKOUT_ frequency as follows: where: f fM = (1 + DRS) TXCLKOUT_ MOD x SDIV Manual Programming of the Spread-Spectrum Divider fM = Modulation frequency DRS = DRS input value (0 or 1) fTXCLKOUT_ = LVDS clock frequency MOD = Modulation coefficient given in Table 8 SDIV = 5-bit SDIV setting, manually programmed by the FC To program the SDIV setting, first look up the modulation coefficient according to the spread-spectrum settings. Table 6. Cable Equalizer Boost Levels BOOST SETTING (0x05 D[3:0]) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 TYPICAL BOOST GAIN (dB) 2.1 2.8 3.4 4.2 5.2 Power-up default (EQS = high) 6.2 7 8.2 9.4 10.7 Power-up default (EQS = low) 11.7 13 Table 7. LVDS and Control Output Spread Rates SS 00 01 10 11 SPREAD (%) No spread spectrum. Power-up default when SSEN = low. Q2% spread spectrum. Power-up default when SSEN = high. No spread spectrum Q4% spread spectrum Table 8. Modulation Coefficients and Maximum SDIV Settings SPREADSPECTRUM SETTING (%) 4 2 MODULATION COEFFICIENT (dec) 208 208 SDIV UPPER LIMIT (dec) 15 30 23 ______________________________________________________________________________________ Gigabit Multimedia Serial Link Deserializer with LVDS System Interface MAX9268 Solve the above equation for SDIV using the desired pixel clock and modulation frequencies. If the calculated SDIV value is larger than the maximum allowed SDIV value in Table 8, set SDIV to the maximum value. The GMSL serializer/MAX9268 include low-power sleep mode to reduce power consumption on the device not attached to the FC (the MAX9268 in LCD applications and the GMSL serializer in camera applications). Set the corresponding remote IC's SLEEP bit to 1 to initiate sleep mode. The GMSL serializer sleeps immediately after setting its SLEEP = 1. The MAX9268 sleeps after serial link inactivity or 8ms (whichever arrives first) after setting its SLEEP = 1. See the Link Startup Procedure section for details on waking up the device for different FC and starting conditions. The FC side device cannot enter into sleep mode. If an attempt is made to program the FC side device for sleep, the SLEEP bit remains 0. Use the power-down mode to bring the FC side device into a low-power state. The MAX9268 includes a power-down mode to further reduce power consumption. Set PWDN low to enter powerdown mode. While in power-down mode, the outputs of the device remain high impedance. Entering power-down mode resets the internal registers of the device. In addition, upon exiting power-down mode, the MAX9268 relatches the state of SSEN, EQS, DRS, and ADD_. The GMSL includes a low-speed configuration link to allow control-data connection between the two devices in the absence of a valid clock input. In either display or camera applications, the configuration link can be used to program equalizer/preemphasis or other registers before establishing the video link. An internal oscillator provides a clock for establishing the serial configuration link between the GMSL serializer and the MAX9268. Set CLINKEN = 1 on the GMSL serializer to turn on the configuration link. The configuration link remains active as long as the video link has not been enabled. The video link overrides the configuration link and attempts to lock when SEREN = 1. and the GMSL serializer/MAX9268 registers or peripherals are ready for programming. For a video-display application with a remote display unit, connect the FC to the GMSL serializer and set CDS = low for both the GMSL serializer and the MAX9268. Table 9 summarizes the four startup cases based on the settings of AUTOS and MS. Case 1: Autostart Mode After power-up or when PWDN transitions from low to high for both the serializer and deserializer, the serial link establishes whether a stable clock is present. The GMSL serializer locks to the clock and sends the serial data to the MAX9268. The MAX9268 then detects activity on the serial link and locks to the input serial data. Case 2: Standby Start Mode After power-up or when PWDN transitions from low to high for both the serializer and deserializer, the MAX9268 starts up in sleep mode, and the GMSL serializer stays in standby mode (does not send serial data). Use the FC and program the serializer to set SEREN = 1 to establish a video link or CLINKEN = 1 to establish the configuration link. After locking to a stable clock (for SEREN = 1) or the internal oscillator (for CLINKEN = 1), the serializer sends a wakeup signal to the MAX9268. The MAX9268 exits sleep mode after locking to the serial data and sets SLEEP = 0. If after 8ms the MAX9268 does not lock to the input serial data, the deserializer goes back to sleep and the internal sleep bit remains set (SLEEP = 1). Case 3: Remote Side Autostart Mode After power-up or when PWDN transitions from low to high, the remote device (MAX9268) starts up and tries to lock to an incoming serial signal with sufficient power. The host side (GMSL serializer) is in standby mode and does not try to establish a link. Use the FC and program the serializer to set SEREN = 1 (and apply a stable clock signal) to establish a video link, or CLINKEN = 1 to establish the configuration link. In this case, the MAX9268 ignores the short wake-up signal sent from the GMSL serializer. Case 4: Remote Side in Sleep Mode After power-up or when PWDN transitions from low to high, the remote device (MAX9268) starts up in sleep mode. The high-speed link establishes automatically after the GMSL serializer powers up with a stable clock signal and sends a wake-up signal to the MAX9268. Use this mode in applications where the MAX9268 powers up before the GMSL serializer. Video-Display Applications Sleep Mode Power-Down Mode Configuration Link Mode Link Startup Procedure Table 9 lists four startup cases for video-display applications. Table 10 lists two startup cases for image-sensing applications. In either video-display or image-sensing applications, the control link is always available after the high-speed data link or the configuration link is established 24 _____________________________________________________________________________________ Gigabit Multimedia Serial Link Deserializer with LVDS System Interface Table 9. Startup Selection for Display Applications (CDS = Low) CASE AUTOS (GMSL SERIALIZER) Low GMSL SERIALIZER POWER-UP STATE Serialization enabled MS (MAX9268) Low MAX9268 POWER-UP STATE Normal (SLEEP = 0) LINK STARTUP MODE Both devices power up with serial link active (autostart). Serial link is disabled and the MAX9268 powers up in sleep mode. Set SEREN = 1 or CLINKEN = 1 in the GMSL serializer to start the serial link and wake up the MAX9268. Both devices power up in normal mode with the serial link disabled. Set SEREN = 1 or CLINKEN = 1 in the GMSL serializer to start the serial link. MAX9268 starts in sleep mode. Link autostarts upon GMSL serializer power-up. Use this case when the MAX9268 powers up before the serializer. MAX9268 1 2 High Serialization disabled High Sleep mode (SLEEP = 1) 3 High Serialization disabled Low Normal (SLEEP = 0) 4 Low Serialization enabled High In sleep mode (SLEEP = 1) SLEEP = 1, VIDEO LINK OR CONFIG LINK NOT LOCKED AFTER 8ms MS PIN SETTING LOW HIGH SLEEP BIT POWER-UP VALUE 0 1 SLEEP WAKE-UP SIGNAL POWER-ON IDLE SIGNAL DETECTED SERIAL PORT LOCKING CONFIG LINK UNLOCKED CONFIG LINK LOCKED CONFIG LINK OPERATING PROGRAM REGISTERS 0 SLEEP SERIAL LINK ACTIVITY STOPS OR 8ms ELAPSES AFTER FC SETS SLEEP = 1 INT CHANGES FROM LOW TO HIGH OR HIGH TO LOW ALL STATES PWDN = LOW OR POWER-OFF PWDN = HIGH, POWER-ON VIDEO LINK LOCKED VIDEO LINK UNLOCKED SEND INT TO GMSL SERIALIZER PRBSEN = 0 POWER-DOWN OR POWER-OFF VIDEO LINK OPERATING PRBSEN = 1 VIDEO LINK PRBS TEST 0 SLEEP Figure 22. State Diagram, CDS = Low (LCD Application) ______________________________________________________________________________________ 25 Gigabit Multimedia Serial Link Deserializer with LVDS System Interface MAX9268 For image-sensing applications, connect the FC to the MAX9268 and set CDS = high for both the GMSL serializer and the MAX9268. The deserializer powers up normally (SLEEP = 0) and continuously tries to lock to a valid serial input. Table 10 summarizes both startup cases, based on the state of the GMSL serializer AUTOS pin. Case 1: Autostart Mode After power-up or when PWDN transitions from low to high, the GMSL serializer locks to a stable input clock and sends the high-speed data to the MAX9268. The deserializer locks to the serial data and outputs the video data and clock. Case 2: Sleep Mode After power-up or when PWDN transitions from low to high, the GMSL serializer starts up in sleep mode. Use the FC to wake up the serializer by sending a GMSL protocol UART frame containing at least three rising edges (e.g., 0x66), at a bit rate no greater than 1Mbps. The low-power wake-up receiver of the serializer detects the wake-up Image-Sensing Applications frame over the reverse control channel and powers up. Reset the sleep bit (SLEEP = 0) of the GMSL serializer using a regular control-channel write packet to power up the device fully. Send the sleep bit write packet at least 500Fs after the wake-up frame. The GMSL serializer goes back to sleep mode if its sleep bit is not cleared within 5ms (min) after detecting a wake-up frame. Applications Information The MAX9268 checks the serial link for errors and stores the number of detected decoding errors in the 8-bit register DECERR (0x0D). If a large number of decoding errors are detected within a short duration, the deserializer loses lock and stops the error counter. The deserializer then attempts to relock to the serial data. DECERR resets upon successful video link lock, successful readout of DECERR (through UART), or whenever autoerror reset is enabled. The MAX9268 does not check for decoding errors during the internal PRBS test and DECERR is reset to 0x00. Error Checking Table 10. Startup Selection for Image-Sensing Applications (CDS = High) CASE 1 AUTOS (GMSL SERIALIZER) Low GMSL SERIALIZER POWER-UP STATE Serialization enabled MAX9268 POWER-UP STATE Normal (SLEEP = 0) Normal (SLEEP = 0) LINK STARTUP MODE Autostart GMSL serializer is in sleep mode. Wake up the serializer through the control channel (FC attached to MAX9268). 2 High Sleep mode (SLEEP = 1) POWER-ON IDLE (REVERSE CHANNEL ACTIVE) NO SIGNAL DETECTED SIGNAL DETECTED SERIAL PORT LOCKING CONFIG LINK UNLOCKED CONFIG LINK LOCKED VIDEO LINK UNLOCKED CONFIG LINK OPERATING PROGRAM REGISTERS PWDN = HIGH, POWER-ON VIDEO LINK LOCKED ALL STATES PWDN = LOW OR POWER-OFF POWER-DOWN OR POWER-OFF PRBSEN = 0 VIDEO LINK OPERATING PRBSEN = 1 VIDEO LINK PRBS TEST Figure 23. MAX9268 State Diagram, CDS = High (Camera Application) 26 _____________________________________________________________________________________ Gigabit Multimedia Serial Link Deserializer with LVDS System Interface ERR Output The MAX9268 has an open-drain ERR output. This output asserts low whenever the number of decoding errors exceeds the error threshold ERRTHR (0x0C) during normal operation, or when at least one PRBS error is detected during the PRBS test. ERR reasserts high whenever DECERR (0x0D) resets due to DECERR readout, video link lock, or autoerror reset. Autoerror Reset The default method to reset errors is to read the respective error registers in the MAX9268 (0x0D, 0x0E). Autoerror reset clears the decoding error counter DECERR and the ERR output ~1Fs after ERR goes low. Autoerror reset is disabled on power-up. Enable autoerror reset through AUTORST (0x06 D6). Autoerror reset does not run when the device is in PRBS test mode. The GMSL serializer/MAX9268 link includes a PRBS pattern generator and bit-error verification function. Set PRBSEN = 1 (0x04 D5) first in the GMSL serializer and then the MAX9268 to start the PRBS test. Set PRBSEN = 0 (0x04 D5) first in the MAX9268 and then the GMSL serializer to exit the PRBS self-test. The MAX9268 uses an 8-bit register (0x0E) to count the number of detected errors. The control link also controls the start and stop of the error counting. During PRBS mode, the device does not count decoding errors and the MAX9268 ERR output reflects PRBS errors only. not required, the FCs can disable the forward and reverse control channel through the REVCCEN and FWDCCEN bits (0x04 D[1:0]) in the GMSL serializer/MAX9268. UART communication across the serial link is prevented and therefore contention between FCs can no longer occur. During dual FC operation, if one of the CDS pins on either side changes state, the link resumes the corresponding state described in the Link Startup Procedure section. As an example of dual FC use in an image-sensing application, the GMSL serializer can be in sleep mode and waiting for wake-up by the MAX9268. After wake-up, the serializer-side FC sets the GMSL serializer's CDS pin low and assumes master control of the serializer's registers. Both the video clock rate (fTXCLKOUT_) and the controlchannel clock rate (fUART) can be changed on-the-fly to support applications with multiple clock speeds. It is recommended to enable the serial link after the video clock stabilizes. Stop the video clock for 5Fs and restart the serial link, or toggle SEREN after each change in the video clock frequency, to recalibrate any automatic settings if a smooth frequency change cannot be guaranteed. The reverse control channel remains unavailable for 350Fs after serial link start or stop. Limit on-the-fly changes in fUART to factors of less than 3.5 at a time to ensure that the device recognizes the UART sync pattern. For example, when lowering the UART frequency from 1Mbps to 100kbps, first send data at 333kbps and then at 100kbps to have reduction ratios of 3 and 3.333, respectively. For quick loss-of-lock notification, the MAX9268 can loop back its LOCK output to the GMSL serializer using the INT signal. Connect the LOCK output to the INT input of the MAX9268. The interrupt output on the GMSL serializer follows the transitions at the LOCK output. Reverse controlchannel communication does not require an active forward link to operate and accurately tracks the LOCK status of the video link. LOCK asserts for video link only and not for the configuration link. The MAX9268 has two open-drain GPIOs available. GPIO1OUT and GPIO0OUT (0x06 D3, D1) set the output state of the GPIOs. The GPIO input buffers are always enabled. The input states are stored in GPIO1 and GPIO0 (0x06 D2, D0). SET GPIO1OUT/GPIO0OUT to 1 when using GPIO1/GPIO0 as an input. MAX9268 Changing the Clock Frequency Self-PRBS Test Usually a single FC is used for GMSL device programming and control-channel communications and is located either on the serializer side for video-display applications or on the deserializer (MAX9268) side for image-sensing applications. In the former case, the CDS pins of the serializer/ deserializer are set to low; in the latter case, they are set to high. However, if the CDS pin of the serializer is low and the same pin on the deserializer is high, then FCs connected at each device are enabled as masters simultaneously. In such a case, the FC on either side communicates with the GMSL serializer and the MAX9268. Contention can occur if the FCs attempt to use the control channel at the same time. The serializer/deserializer do not in themselves provide a way to avoid contention. The fact that an acknowledge is not received when contention occurs can be used to trigger a retry. Alternatively, a higher layer protocol can be implemented to avoid contention. In addition, if UART communication across the serial link is Microcontrollers on Both Sides of the GMSL Link (Dual C Control) LOCK Output Loopback GPIOs ______________________________________________________________________________________ 27 Gigabit Multimedia Serial Link Deserializer with LVDS System Interface MAX9268 Both the GMSL serializer and the MAX9268 have programmable device addresses. This allows multiple GMSL devices along with I2C peripherals to coexist on the same control channel. The serializer device address is stored in registers 0x00 of each device, while the deserializer device address is stored in register 0x01 of each device. To change the device address, first write to the device whose address changes (register 0x00 of the GMSL serializer for serializer device address change, or register 0x01 of the MAX9268 for deserializer device address change). Then write the same address into the corresponding register on the other device (register 0x00 of the MAX9268 for serializer device address change, or register 0x01 of the GMSL serializer for deserializer device address change). ADD0 and ADD1 are 3-level inputs, which set the device addresses stored in the MAX9268 (Table 2). Set the desired device addresses by connecting ADD0/ADD1 through a pullup resistor to IOVDD, a pulldown resistor to GND, or to high impedance. For digital control, use threestate logic to drive the 3-level logic inputs. ADD0/ADD1 set the device addresses in the MAX9268 only and not the GMSL serializer. Set the GMSL serializer's ADD0/ADD1 inputs to the same settings as the MAX9268; alternatively, write to registers 0x00 and 0x01 of the GMSL serializer to reflect any changes made due to the 3-level inputs. Both open-drain lines require pullup resistors to provide a logic-high level. There are trade-offs between power dissipation and speed, and a compromise made in choosing pullup resistor values. Every device connected to the bus introduces some capacitance even when the device is not in operation. I2C specifies 300ns rise times to go from low to high (30% to 70%) for fast mode, which is defined for data rates up to 400kbps (see the I2C specifications in the AC Electrical Characteristics section for details). To meet the fast-mode rise-time requirement, choose the pullup resistors such that rise time tR = 0.85 x RPULLUP x CBUS < 300ns. The waveforms are not recognized if the transition time becomes too slow. The MAX9268 supports I2C/UART rates up to 1Mbps. I2C/UART Programming the Device Addresses AC-coupling isolates the receiver from DC voltages up to the voltage rating of the capacitor. Four capacitors (two at the serializer output and two at the deserializer input) are needed for proper link operation and to provide protection if either end of the cable is shorted to a high voltage. AC-coupling blocks low-frequency ground shifts and low-frequency common-mode noise. Voltage droop and the digital sum variation (DSV) of transmitted symbols cause signal transitions to start from different voltage levels. Because the transition time is finite, starting the signal transition from different voltage levels causes timing jitter. The time constant for an AC-coupled link needs to be chosen to reduce droop and jitter to an acceptable level. The RC network for an AC-coupled link consists of the CML receiver termination resistor (RTR), the CML driver termination resistor (RTD), and the series AC-coupling capacitors (C). The RC time constant for four equal-value series capacitors is (C x (RTD + RTR))/4. RTD and RTR are required to match the transmission line impedance (usually 100I). This leaves the capacitor selection to change the system time constant. Use at least 0.2FF high-frequency surface-mount ceramic capacitors, with sufficient voltage rating to withstand a short to battery, to pass the lower speed reverse control-channel signal. Use capacitors with a case size less than 3.2mm x 1.6mm to have lower parasitic effects to the high-speed signal. The MAX9268 uses a 3.0V to 3.6V VAVDD and VDVDD. All single-ended inputs and outputs on the MAX9268 derive power from a 1.7V to 3.6V VIOVDD, which scales with IOVDD. Proper voltage-supply bypassing is essential for high-frequency circuit stability. AC-Coupling Selection of AC-Coupling Capacitors 3-Level Inputs for Default Device Address Choosing I2C/UART Pullup Resistors Power-Supply Circuits and Bypassing Interconnect for CML typically has a differential impedance of 100I. Use cables and connectors that have matched differential impedance to minimize any impedance discontinuities. Twisted-pair and shielded twisted-pair cables tend to generate less EMI due to magnetic-field canceling effects. Balanced cables pick up noise as common mode rejected by the CML receiver. Table 11 lists the suggested cables and connectors used in the GMSL link. Cables and Connectors 28 _____________________________________________________________________________________ Gigabit Multimedia Serial Link Deserializer with LVDS System Interface Separate the digital signals and CML/LVDS high-speed signals to prevent crosstalk. Use a four-layer PCB with separate layers for power, ground, CML/LVDS, and digital signals. Layout PCB traces close to each other for a 100I differential characteristic impedance. The trace dimensions depend on the type of trace used (microstrip or stripline). Note that two 50I PCB traces do not have 100I differential impedance when brought close together because the impedance goes down when the traces are brought closer. Route the PCB traces for a CML/LVDS channel (there are two conductors per CML/LVDS channel) in parallel to maintain the differential characteristic impedance. Avoid vias. Keep PCB traces that make up a differential pair equal length to avoid skew within the differential pair. Board Layout The MAX9268 ESD tolerance is rated for Human Body Model, IEC 61000-4-2, and ISO 10605. The ISO 10605 and IEC 61000-4-2 standards specify ESD tolerance for electronic systems. CML/LVDS I/O are tested for ISO 10605 ESD protection and IEC 61000-4-2 ESD protection. All pins are tested for the Human Body Model. The Human Body Model discharge components are CS = 100pF and RD = 1.5kI (Figure 24). The IEC 61000-4-2 discharge components are CS = 150pF and RD = 330I (Figure 25). The ISO 10605 discharge components are CS = 330pF and RD = 2kI (Figure 26). ESD Protection MAX9268 Table 11. Suggested Connectors and Cables for GMSL VENDOR JAE Electronics, Inc. Nissei Electric Co., Ltd. CONNECTOR MX38-FF GT11L-2S CABLE A-BW-Lxxxxx F-2WME AWG28 Dacar 538 HIGHVOLTAGE DC SOURCE CHARGE-CURRENTLIMIT RESISTOR CS 150pF RD 330I DISCHARGE RESISTANCE STORAGE CAPACITOR DEVICE UNDER TEST Rosenberger D4S10A-40ML5-Z Hochfrequenztechnik GmbH Figure 25. IEC 61000-4-2 Contact Discharge ESD Test Circuit 1MI CHARGE-CURRENTLIMIT RESISTOR CS 100pF RD 1.5kI DISCHARGE RESISTANCE STORAGE CAPACITOR DEVICE UNDER TEST HIGHVOLTAGE DC SOURCE CHARGE-CURRENTLIMIT RESISTOR CS 330pF RD 2kI DISCHARGE RESISTANCE STORAGE CAPACITOR DEVICE UNDER TEST HIGHVOLTAGE DC SOURCE Figure 24. Human Body Model ESD Test Circuit Figure 26. ISO 10605 Contact Discharge ESD Test Circuit ______________________________________________________________________________________ 29 Gigabit Multimedia Serial Link Deserializer with LVDS System Interface MAX9268 Table 12. Register Table (see Table 1) REGISTER ADDRESS 0x00 BITS D[7:1] D0 0x01 D[7:1] D0 NAME SERID -- DESID -- VALUE XXXXXXX 0 XXXXXXX 0 00 D[7:6] SS 01 10 11 D5 0x02 D4 -- AUDIOEN 0 0 1 00 D[3:2] PRNG 01 10 11 00 D[1:0] SRNG 01 10 11 00 01 D[7:6] 0x03 D5 D[4:0] -- SDIV AUTOFM 10 11 0 00000 XXXXX FUNCTION Serializer device address. Power-up default address determined by ADD0 and ADD1 (see Table 2). Reserved Deserializer device address. Power-up default address determined by ADD0 and ADD1 (see Table 2). Reserved No spread spectrum. Power-up default when SSEN = low. Q2% spread spectrum. Power-up default when SSEN = high. No spread spectrum Q4% spread spectrum Reserved Disable I2S channel Enable I2S channel 12.5MHz to 25MHz pixel clock 25MHz to 50MHz pixel clock 50MHz to 104MHz pixel clock Automatically detect the pixel clock range 0.5Gbps to 1Gbps serial-data rate 1Gbps to 2Gbps serial-data rate 2Gbps to 3.125Gbps serial-data rate Automatically detect serial-data rate Calibrate spread-modulation rate only once after locking Calibrate spread-modulation rate every 2ms after locking Calibrate spread-modulation rate every 16ms after locking Calibrate spread-modulation rate every 256ms after locking Reserved Autocalibrate sawtooth divider Manual SDIV setting. See the Manual Programming of Spread-Spectrum Divider section. 00000 0 00 11 11 0 1 00, 01 DEFAULT VALUE XX00XX0 0 XX01XX0 0 30 _____________________________________________________________________________________ Gigabit Multimedia Serial Link Deserializer with LVDS System Interface Table 12. Register Table (see Table 1) (continued) REGISTER ADDRESS BITS D7 D6 D5 NAME LOCKED OUTENB PRBSEN VALUE 0 1 0 1 0 1 0 D4 0x04 SLEEP 1 00 D[3:2] INTTYPE 01 10, 11 D1 REVCCEN 0 1 0 1 0 D7 I2CMETHOD 1 00 D[6:5] HPFTUNE 01 10 11 D4 PDHF 0 1 0000 0001 0x05 0010 0011 0100 0101 D[3:0] EQTUNE 0110 0111 1000 1001 1010 1011 11XX LOCK output is low LOCK output is high Enable outputs Disable outputs Disable PRBS test Enable PRBS test Normal mode. Default value depends on CDS and MS pin values at power-up). Activate sleep mode. Default value depends on CDS and MS pin values at power-up). Base mode uses I2C peripheral interface Base mode uses UART peripheral interface Base mode peripheral interface disabled Disable reverse control channel to serializer (sending) Enable reverse control channel to serializer (sending) Disable forward control channel from serializer (receiving) Enable forward control channel from serializer (receiving) I2C conversion sends the register address Disable sending of I2C register address (commandbyte-only mode) 7.5MHz equalizer highpass cutoff frequency 3.75MHz cutoff frequency 2.5MHz cutoff frequency 1.87MHz cutoff frequency High-frequency boosting enabled High-frequency boosting disabled 2.1dB equalizer boost gain 2.8dB equalizer boost gain 3.4dB equalizer boost gain 4.2dB equalizer boost gain 5.2dB equalizer boost gain. Power-up default when EQS = high. 6.2dB equalizer boost gain 7dB equalizer boost gain 8.2dB equalizer boost gain 9.4dB equalizer boost gain 10.7dB equalizer boost gain. Power-up default when EQS = low. 11.7dB equalizer boost gain 13dB equalizer boost gain Do not use 0100, 1001 0 01 0 1 00 FUNCTION DEFAULT VALUE 0 (read only) 0 0 MAX9268 0, 1 D0 FWDCCEN 1 ______________________________________________________________________________________ 31 Gigabit Multimedia Serial Link Deserializer with LVDS System Interface MAX9268 Table 12. Register Table (see Table 1) (continued) REGISTER ADDRESS BITS D7 D6 D5 D4 0x06 D3 D2 D1 D0 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E D[7:0] D[7:0] D[7:0] D[7:0] D[7:0] D[7:0] D[7:0] D[7:0] D7 0x12 D[6:0] 0x13 D[7:5] D[4:0] MCLKDIV -- -- NAME -- AUTORST DISINT INT GPIO1OUT GPIO1 GPIO0OUT GPIO0 -- -- -- -- -- ERRTHR DECERR PRBSERR MCLKSRC VALUE 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 01010100 00110000 11001000 00010010 00100000 XXXXXXXX XXXXXXXX XXXXXXXX 0 1 0000000 XXXXXXX XXX 10000 Reserved Do not automatically reset error registers and outputs Automatically reset error registers and outputs Enable interrupt transmission to serializer Disable Interrupt transmission to serializer INT input = low (read only) INT input = high (read only) Output low to GPIO1 Output high to GPIO1 GPIO1 is low GPIO1 is high Output low to GPIO0 Output high to GPIO0 GPIO0 is low GPIO0 is high Reserved Reserved Reserved Reserved Reserved Error threshold for decoding errors. ERR = low when DECERR > ERRTHR. Decoding error counter. This counter remains zero while the device is in PRBS test mode. PRBS error counter MCLK derived from PCLK (see Table 5) MCLK derived from internal oscillator MCLK disabled MCLK divider Reserved Reserved FUNCTION DEFAULT VALUE 0 0 0 0 (read only) 1 1 (read only) 1 1 (read only) 01010100 00110000 11001000 00010010 00100000 00000000 00000000 (read only) 00000000 (read only) 0 0000000 (read only) 10000 32 _____________________________________________________________________________________ Gigabit Multimedia Serial Link Deserializer with LVDS System Interface Table 12. Register Table (see Table 1) (continued) REGISTER ADDRESS BITS D[7:6] D5 NAME -- FORCELVDS VALUE 00 0 1 0 D4 DCS 1 0x14 D3 D2 DISCNTL1 DISRES 0 1 0 1 00 D[1:0] ILVDS 01 10 11 0x1E D[7:0] D[7:5] 0x1F D4 D[3:0] X = Don't care. ID -- CAPS REVISION 00000100 000 0 1 XXXX Reserved Normal operation Force LVDS outputs low Normal driver current for CMOS outputs (WS, SCK, SD/ CNTL0, CNTL1, CNTL2/MCLK) Strong driver current for CMOS outputs (WS, SCK, SD/ CNTL0, CNTL1, CNTL2/MCLK) Serial-data bit 27 is mapped to CNTL1 CNTL1 forced low Serial-data bit 27 is mapped to RES RES bit forced low 1.75mA LVDS current 3.5mA LVDS current Do not use 7mA LVDS current Device identifier (MAX9268 = 0x04) Reserved Not HDCP capable HDCP capable Device revision 00000100 (read only) 000 (read only) 0 (read only) (read only) 01 FUNCTION DEFAULT VALUE 00 0 MAX9268 0 0 0 ______________________________________________________________________________________ 33 Gigabit Multimedia Serial Link Deserializer with LVDS System Interface MAX9268 Typical Application Circuit TXCLK+/TX0+/TO TX2+/GPU RXCLKIN+/RXIN0+/TO RXIN2+/CDS AUTOS LMN1 ECU MAX9249 TCLKOUT+/TXOUT0+/TO TXOUT2+/45kI 45kI CDS RXCLK+/RX0+/TO RX2+/- LMN0 MAX9268 5kI OUT+ UART Tx Rx LFLT INT MS WS SCK SD RX/SDA TX/SCL LFLT INT MS WS SCK SD/CNTL0 OUT- 5kI IN+ IN50kI 50kI LOCK WS SCK SD/CNTL0 SCK DISPLAY APPLICATION IN SD INT RX/SDA TX/SCL DISPLAY TO PERIPHERALS SCL SDA WS MAX9850 AUDIO PLL OUT MCLK NOTE: NOT ALL PULLUP/PULLDOWN RESISTORS ARE SHOWN. SEE PIN DESCRIPTION FOR DETAILS. Chip Information PROCESS: CMOS Package Information For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE 48 TQFP-EP PACKAGE CODE C48E+8 OUTLINE LAND PATTERN NO. NO. 21-0065 90-0138 34 _____________________________________________________________________________________ Gigabit Multimedia Serial Link Deserializer with LVDS System Interface Revision History REVISION NUMBER 0 1 2 REVISION DATE 4/10 5/10 1/11 Initial release Changed conditions for LVDS output enable/disable times and SCK jitter limits in the AC Electrical Characteristics table Added Patent Pending to Features DESCRIPTION PAGES CHANGED -- 5 1 MAX9268 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 35 2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc. |
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